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TC9470FN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9470FN
- Modulation DA Converter with Built-in 8-Times Oversampling Digital Filter/Dynamic Digital Bass Boost/Analog Filter
The TC9470FN is a second-order - modulation system 1-bit DA converter incorporating an 8-times oversampling digital filter, dynamic digital bass boost function for use with compressor operations and an analog filter developed for digital audio equipment. Because the IC includes an analog filter, it can output a direct analog waveform, thus reducing the size and cost of the DA converter.
Features
* * * * * * * * * * * * * Built-in 8-times oversampling digital filter Low-voltage operations (2.4 V) possible Built-in digital de-emphasis filter Built-in dynamic digital bass boost function In serial control mode, output amplitude can be set in 4096 steps of resolution using microcontroller commands In parallel control mode, soft mute can be set for the output signal in 64 steps in 23 ms Built-in LR common digital zero detection output circuit Sampling frequency: 44.1 kHz Supports 384 fs/256 fs (automatic switching) DA converter oversampling ratio (OSR): 192 fs (at 384 fs) Stereo/monaural output selection possible Built-in third-order analog filter The digital filter and DA converter characteristics are shown on the next page Weight: 0.14 g (typ.)
Digital Filter
Digital Filter Standard operation 8 fs Passband Ripple 0.11dB Transient Bandwidth 20 k to 24.1 kHz Attenuation -26dB or less
DA Converter (VDD = 2.7 V)
OSR Standard operation 192 fs Noise Distortion -82dB (typ.) S/N Ratio 90dB (typ.)
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Pin Connection
VDD T1
P/ S
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
LRCK BCK DATA DBB2 ATT (DBB1) SHIFT (EMP) LATCH (SM) VDX XO XI GNDX MCK
VDA RO GNDA VR GNDA LO VDA ZD GNDD
Block Diagram
(DBB1) (EMP) (SM) LRCK BCK DATA DBB2 ATT SHIFT LATCH VDX 24 23 22 21 20 19 18 17
XO 16
XI 15
GNDX MCK 14 13
Data interface circuit Dynamic bus boost circuit +
Microcontroller interface circuit
Oscillator circuit Timing generator
Digital filter circuit, de-emphasis filter circuit, attenuator circuit - modulator circuit Output circuit Analog filter Output circuit Analog filter 6 7 8 9 10 VDA 11 12
Test circuit
1 VDD
2 T1
3
P/ S
4 VDA
5
RO GNDA VR GNDA LO
ZD GNDD
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Pin Function
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Symbol VDD T1
P/ S
I/O I I O O O O I Crystal oscillator connecting pins. Digital block power supply pin Test pin. Always set to "Low" level. Parallel/serial mode select pin Analog power supply pin
Function
Remarks
VDA RO GNDA VR GNDA LO VDA ZD GNDD MCK GNDX XI
Right channel analog signal output pin Analog GND pin Reference voltage pin Analog GND pin Left channel analog signal output pin Analog power supply pin Zero data detection output pin common to left and right channels Digital GND pin System clock output pin Crystal oscillator GND pin
Generate the clock required by the system. 16 17 18 XO VDX LATCH (SM) SHIFT (EMP) ATT (DBB1) DBB2 DATA BCK LRCK O I Crystal oscillator power supply pin In serial mode, data latch signal input pin In parallel mode, soft mute control pin In serial mode, shift clock input pin In parallel mode, de-emphasis filter control pin In serial mode, data input pin In parallel mode, dynamic bass boost control pin 1 In parallel mode, dynamic bass boost control pin 2 Audio data input pin Bit clock input pin LR clock input pin
XI
XO
Schmidt input
19
I
Schmidt input
20 21 22 23 24
I I I I I
Schmidt input
Schmidt input Schmidt input Schmidt input
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Description of Block Operations
1. Crystal Oscillator Circuit and Timing Generator
The clock required for internal operations is generated by connecting a crystal and condensers as shown in the diagram below. The IC will also operate when a system clock is input from an external source through the XI pin (pin 15). However, in this situation, due consideration must be given to the fact that waveform characteristics, such as jitter and rising/falling characteristics of the system clock, significantly affect the DA converter's noise distortion and the S/N ratio.
To internal circuit
GNDX CL
XI X'tal
MCK XO VDX 16.9344 MHz CL CL = 10 to 33 pF
Use a crystal with a low CI value and favorable start-up characteristics.
Figure 1
Crystal Oscillator Circuit Configuration (when in the 384 fs mode)
The timing generator generates the clocks and process timing signals required for such functions as digital filtering and de-emphasis filtering.
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2. Data Input Circuit
DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge. It is consequently necessary for the DATA and LRCK signals to be synchronized and input on the BCK signal falling edge as indicated in the timing example below. Also, as DATA has been designed so that the 16 bits before the change point of LRCK are regarded as valid data, the data must be input with Right-justified mode when the BCK is 48 fs or 64 fs, as shown in Figure 2a.
L-ch R-ch
LRCK
BCK 10 9 8 7 6 5 4 3 2 LSB MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 LSB
DATA
MSB 15
14
13
12
11
Figure 2a Example of Input Timing Chart
LRCK R-ch
L-ch
BCK
DATA
M L S 15 14 13 12 11 10 9 8 7 6 5 4 3 2 S B B
M L S 15 14 13 12 11 10 9 8 7 6 5 4 3 2 S B B
Invalid data
Invalid data
Figure 2b
Example of Input Timing Chart
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3. Digital Filter
The 8-times oversampling IIR digital filter eliminates the noise returned from outside the bandwidth during standard operations.
Table 1
Set Mode Standard operations
Basic Characteristics of Digital Filter
Passband Ripple 0.11dB Transient Bandwidth 20 k to 24.1 kHz Attenuation -26dB or less
The characteristics of the digital filter frequencies are shown below.
0.000 -10.00 -20.00 -30.00
-0.00 -0.10 -0.20 -0.30
(dB)
Gain
-60.00 -70.00 -80.00 -90.00 -100.0 0 44.1 88.2 132.3 176.4
Gain
-50.00
(dB)
-40.00
-0.40 -0.50 -0.60 -0.70 -0.80 -0.90 -1.00 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 0.65dB
Frequency (kHz)
Frequency (kHz)
Figure 3
4. De-Emphasis Filter
Digital Filter Frequency Characteristics
ON/OFF is controlled in the parallel mode ( P/ S = "H") with the SHIFT (EMP) pin (pin 19). This is set in the serial mode ( P/ S = "L") with a microcontroller or other equipment. (refer to 10.2 microcontroller setting mode for further details on serial mode settings.)
Table 2
De-Emphasis Filter Settings (when in the parallel mode)
Shift (EMP) Pin De-emphasis filter H ON L OFF
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The digitalization of the de-emphasis filter eliminates the need for such external components as resistors, condensers and analog switches. In addition to this, the coefficients are aligned to reduce error in the de-emphasis filter characteristics. The filter structure and characteristics are shown below.
Input data + Z-1 a1 b1
1/T1 1/T2
b0
+
|G (j)|
(b + b1Z -1) Transfer function : H (Z) = 0 (1 - a1Z -1 )
T1 = 50 s, T2 = 15 s
Figure 4
IIR Digital De-Emphasis Filter
Figure 5
Filter Characteristics
5. Dynamic Digital Bass Boost Circuit
ON/OFF for the dynamic digital bass boost is controlled in the parallel mode ( P/ S = "H") with the DBB1 pin (pin 20) and the DBB2 pin (pin 21). This is set in the serial mode ( P/ S = "L") with a microcontroller or other equipment. (refer to 10.2 microcontroller setting mode for further details on serial mode settings.) A block diagram for the dynamic bass boost circuit is shown in Figure 6.
INPUT OUTPUT
+
L.P.F SERIAL ATTENUATOR Coefficient length: 7 bits COMPRESSOR BLOCK
Figure 6
Dynamic Digital Bass Boost Circuit Block
The compressor's compression ratio when in the control mode for the parallel mode is shown below.
Table 3
Compressor Compression Ratio (when in the parallel mode)
DBB max DBB MID 18dB 12dB
The compressor's compression characteristics are as follows:
Table 4
Compressor Compression Characteristics (when in the parallel mode)
DBB max DBB MID -36dB -24dB
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The compressor I/O characteristics for the dynamic digital bass boost are shown in Figure 7.
0 -10
EFS = "L"
(dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 EFS = "H"
Compressor gain output
Input level
(dB)
Figure 7
Dynamic Digital Bass Boost Compressor I/O Characteristics
The bass boost settings when in the parallel mode are shown below.
Table 5
Bass Boost Mode Settings
MODE 1 MODE 2 L H MODE 3 H L MODE 4 H H
DBB1 (pin 20) DBB2 (pin 21)
L L
MODE 1: DBB OFF MODE 2: DBB MID MODE 3: DBB max MODE 4: DBB max + HB
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The bus boost characteristics are shown in Figure 8.
30 25 20
30 25 20
Response (dB)
Response (dB)
15 10 5 0 -5 -10 0.01
15 10 5 0 -5 -10 0.01
0.1
1
10
100
0.1
1
10
100
Frequency (kHz)
Frequency (kHz)
a) Vin = -36dB input, DBB OFF, 1 kHz = 0dB.
b) Vin = -20dB input, DBB OFF, 1 kHz = 0dB. Compressor characteristics MID: EFS = "L" (-24dB) max: EFS = "H" (-36dB) MAGA: EFS = "H" (-36dB)
30 25 20
Response (dB)
15 10 5 0 -5 -10 0.01 OFF MID max + HB MEGA + HB
0.1
1
10
100
Frequency (kHz)
c) Vin = 0dB input, DBB OFF, 1 kHz = 0dB. Compressor's compression characteristics MID: EFS = "L" (-24dB) max: EFS = "H" (-36dB) MAGA: EFS = "H" (-36dB)
Figure 8
Dynamic Bass Boost Frequency Characteristics (VDD = 2.7 V)
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6. DA Conversion Circuit
The IC incorporates a second-order - modulation DA converter for two channels (simultaneous output type). The internal structure of this is shown in Figure 9.
Data X (Z) + Z-1 Limiter + Z 2
-1
Q +
Y (Z)
Output data
(bit-stream 1-bit DA conversion data) -
-
Second-order - converter: Y (Z) = X (Z) + (1 - Z-1)2 Q (Z)
Figure 9 - Modulation DA Converter
The - modulation clock has been designed to operate at 192 fs (when 384 fs). The noise shaping characteristics are shown in Figure 10.
10dB
Noise power
(dB)
0
500 k
1M
Frequency (Hz)
Figure 10
7. Data Output Circuit
Noise Shaping Characteristics
The output circuit is equipped with a third-order analog low-pass filter. This enables direct analog signals to be acquired from the IC's RO (pin 5) and LO (pin 9) output pins.
PDM signals
RO (LO)
VR
Figure 11
Analog Filter Circuit
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8. Soft Mute Circuit
The IC is equipped with a soft mute function, and this enables a soft mute to be set for the DA converter output by switching the SM pin (pin 18) from the "L" level to the "H" level when in the parallel mode ( P/ S = "H"). The soft mute's ON/OFF function and the DA converter output are shown in Figure 12. The Soft mute ON/OFF control function is disabled during level transition.
SM Pin Input DA Converter Output Level
1 64 1 64
Off
On
Off
Approximately 23 ms
Approximately 23 ms
Figure 12
Changes in the Soft Mute DA Converter Output Level
9. Common Left Channel/Right Channel Digital Zero Data Detection Output Circuit
The IC is equipped with a common left channel/right channel digital zero data detection output circuit, and the ZD pin (pin 11) is switched from "L" to "H" when data for both the left channel and the right channel becomes zero data for approximately 350 ms or longer. This is fixed at "L" when the data for the left channel and right channel is not zero data.
10. Description of Internal Control Signals
The P/ S pin can be used to switch between the parallel mode ( P/ S pin = "H" in DC setting mode) and the serial mode ( P/ S pin = "L" with the microcontroller interface function).
10.1 Parallel Mode ( P/ S = "H": DC setting mode)
Pins 18, 19, 20 and 21 are used as the mode setting pins shown in the table below when in the parallel mode.
Table 6
Pin No. 18 19 20 21
Pin Names at the Parallel Mode
Pin Description Soft mute control pin De-emphasis control pin Digital bass boost mode control pin 1 Digital bass boost mode control pin 2
Pin Name SM EMP DBB1 DBB2
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10.2 Serial Mode ( P/ S = "L": microcontroller setting mode)
It is possible to make the various settings with a microcontroller when in the serial mode. Pins 18, 19 and 20 are used as the command input pins shown in the table below when in the serial mode.
Table 7
Pin No. 18 19 20
Pin Names at the Serial Mode
Pin Description Data latch signal input pin Shift clock signal input pin Data input pin
Pin Name LATCH SHIFT ATT
The LATCH signals and ATT signals are loaded to the LSI internal shift registers on the SHIFT signal rising edge. It is consequently necessary for the data input from the ATT pin on the shift signal rising edge to be valid as indicated in the timing example in Figure 13. It is also necessary for the LATCH pulse to rise at least 1.5 s after the final clock rising edge input from the SHIFT pin. Operating the shift clock with LATCH low destabilizes the internal state, which may lead to malfunctions, so it must therefore be set to the low level after loading D7 to the register.
LATCH
SHIFT
ATT
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
A = 1.5 s or higher, B = 1.5 s or higher
Figure 13 Example of Data Setting Timing in the Serial Mode
The various control settings when in the serial mode are shown in the table below. Ensure that all control bits are set when the power supply is turned on.
Table 8
Serial Mode Control Settings
Control Signals MODE 1 0 AT11 AT10 AT09 AT08 AT07 AT06 AT05 AT04 AT03 AT02 AT01 AT00 MODE 2 1 0 EMP MONO CHS RLS EFS DOFF MODE 3 1 1 DBB1 DBB2 DBB3 BMUTE TCA TCR
Serial Input Data D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
AT11 to AT00: Attenuation level setting EMP: De-emphasis ON/OFF switch MONO, CHS: Stereo/monaural switch RLS: LRCK polarity switch EFS: Dynamic circuit compression characteristics switch DOFF: Dynamic circuit ON/OFF switch DBB1, DBB2: Digtal bass boost mode setting DBB3: DBB MEGA max setting BMUTE: Bass boost mute TCA: Attack time switch TCR: Recovery time switch
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10.2.1 Setting Mode 1
Serial setting mode 1 is enabled when D12 = "L". (1) Digital attenuator The digital attenuation command is enabled when D12 = L. The attenuation data can be set in 4096 different ways (coefficient: 12 bit, maximum attenuation: -72.245dB). The relationship with the command's output is shown below.
Table 9
Attenuation Data/Audio Data Output
Attenuation Data AT [11:00] FFFH FFEH FFBH *** C80H *** 640H *** 002H 001H 000H Audio Output -0.000dB -0.002dB -0.004dB *** -2.142dB *** -8.163dB *** -66.224dB -72.245dB -
001 (HEX) to FFE (HEX): The attenuation value is obtained with the following equation. ATT = 20 og (input data/4095) dB Example: When the attenuation data is EA0H ATT = 20 og (4000/4095) dB = -0.204dB If an input level is set to -48dB or less when it is set as the amount (-72.245dB) of the maximum attenuation, the target effective attenuation data of digital attenuator of TC9470FN will be lost. The output data is set to "0" when an input level is set to -48dB or less. An effective input level is decided by the following formula. Effective input data = -[120dB + Attenuation level (dB)]
10.2.2 Setting Mode 2
Serial setting mode 2 is enabled when D12 = "H" and D11 = "L". (1) Digital de-emphasis filter Controlled with EMP.
Table 10
Digital De-Emphasis Filter Setting
EMP L OFF H ON
De-emphasis filter
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(2) Stereo/monaural output channel settings Set with MONO and CHS.
Table 11
MONO CHS L, R-ch output
Stereo, Monaural and Channel Select Settings
L (Note) Stereo output H L L-ch monaural output H H R-ch monaural output
Note: "H" or "L" (3) LRCH (channel clock) polarity switch settings Set with RLS.
Table 12
RLS Data input
LRCK Polarity Switch Settings
L H L-ch data when LRCK = "L"
R-ch data when LRCK = "L"
(4)
Compressor's compression characteristics switch settings Set with EFS.
Table 13
Compressor Compression Characteristics (compression ratio) Settings
EFS L -24dB 12dB H -36dB 18dB
Compressor's compression characteristics Compressor compression ratio
Compressor's compression characteristics and compression ratio are shown in Figure 7. (5) Dynamic circuit ON/OFF switch settings Set with DOFF.
Table 14
Dynamic Circuit ON/OFF Switch Settings
DOFF Dynamic circuit L ON H OFF
The dynamic circuit's ON/OFF switch settings become invalid when DBB3 is set to "H" in the following mode 2 settings. The amount of boost when the dynamic circuit is OFF is shown in table 15.
Table 15
Amount of Boost when the Dynamic Circuit is OFF
Amount of Boost MID max 10.6dB 15.2dB
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10.2.3 Setting Mode 3
Serial setting mode 3 is enabled when D7 = "H" and D6 = "H". (1) Digital bass boost mode settings Set with DBB1, DBB2 and DBB3.
Table 16
MODE 1 DBB1 DBB2 DBB3 L L L or H
Bass Boost Mode Settings
MODE 2 L H L or H MODE 3 H L L or H MODE 4 H H L or H
The DBB3 settings are as follows. DBB3 = "L" DBB3 = "H" MODE 1': DBB OFF MODE 1: DBB OFF MODE 2': DBB max MODE 2: DBB MID MODE 3': DBB MEGA max MODE 3: DBB max MODE 4': DBB MEGA max + HB MODE 4: DBB max + HB (2) Bass boost mute setting Set with BMUTE. The bass boost mute to be set for bass boost signal by switching the BMUTE from the "L" level to the "H" level.
Table 17
BMUTE
Bass Boost Mute Setting
L OFF H ON
Bass boost mute
Time constant of bass boost mute: Approximately 3.8 ms (3) Attack time/recovery time switch settings Set with TCA for attack time and TCR for recovery time.
Table 18
TCA Attack time
Attack Time Settings
L 6.3 ms H 24.3 ms
Table 19
TCA
Recovery Time Settings
L 12.3 s H 24.6 s
Recovery time
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Maximum Ratings (Ta = 25C)
Characteristics Symbol VDD Power supply voltage VDA VDX Input voltage Power dissipation Operating temperature Storage temperature Vin PD Topr Tstg Rating -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -0.3 to VDD + 0.3 200 -15 to 50 -55 to 150 V mW C C V Unit
Electrical Characteristics
DC Characteristics
Characteristics
(unless otherwise specified, Ta = 25C, VDD = VDX = VDA = 2.7 V)
Symbol VDD
Test Circuit
Test Condition
Min 2.4
Typ. 2.7 2.7 2.7 4.0
Max 3.5 3.5 3.5 5.5 VDD VDD x 0.3 10
Unit
Operating power supply voltage
VDX VDA
Ta = -15 to 50C
2.4 2.4
V
Current consumption "H" level Input voltage "L" level Input current "H" level "L" level
IDD VIH
XI = 16.9344 MHz VDD = VDX = 2.4 V
VDD x 0.7 0
mA
VIL IIH IIL
V
-10
A
AC Characteristics (oversampling ratio = 192 fs)
Characteristics Noise distortion S/N ratio Dynamic range Crosstalk Analog output level Operating frequency Input frequency Rise time Fall time Delay time Symbol THD + N S/N DR CT Aout fopr fLR fBCK tr tf td Test Circuit 1 1 1 1 1 Test Condition 1 kHz sine wave, full-scale input VDD = VDX = VDA = 2.7 V VDD = VDX = VDA = 2.7 V 1 kHz sine wave, -60dB input conversion 1 kHz sine wave, full-scale input 1 kHz sine wave, full-scale input VDD = VDX = VDA = 2.7 V VDD = VDX = VDA 2.4 V LRCK duty cycle = 50% BCK duty cycle = 50% LRCK, BCK pins (10% to 90%) BCK edge LRCK, DATA Min 85 85 11 1.4 Typ. -82 90 90 -90 685
16.9344
Max -77 -80 2.9 15 15 50
Unit dB dB dB dB mVrms MHz kHz MHz ns ns ns
44.1 2.1168
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* Test circuit 1: With the use of a sample application circuit
LOUT DATA BCK Application circuit example LRCK ROUT MCK 20 kHz Ideal LPF Distortion factor gauge
SG
SG: Anritsu: MG-22A or equivalent LPF: Shibasoku: Built-in 725C distortion factor gauge filter Distortion: Shibasoku: 725C or equivalent
Parameter Measured THD + N, CT S/N, DR Distortion Factor Gauge Filter Setting A Weight OFF ON
A weight: IEC-A or equivalent
*
AC characteristics stipulated point (input signal stipulation: LRCK, BCK, DATA)
10% 90% tf 10% 90% tf
BCK
50% 50% td
DATA 50% td
LRCK
Application Circuit
The following diagram is for reference purposes only and does not guarantee operations.
MCK 30 pF 16.9344 M 100 F 30 pF 2.7 V 2.7 V GNDX XI XO VDX LATCH (SM) SHIFT (EMP) ATT (DBB1) (DBB2) DATA BCX LRCK TC9470FN GNDD ZD VDA LO GNDA VR GNDA RO VDA
P/S
ZD 2.7 V 220 2200 pF 100 F 10 k 10 k 2.7 V L-ch Analog OUT
22 F 100 F
XI EMPH TC9236AF Single-chip processor Aout for CD players BCK CHCK
220 2200 pF
R-ch Analog OUT
2.7 V
T1 VDD
100 F
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Package Dimensions
Weight: 0.14 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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